Teymourzadeh, Rozita and Othman, Masuri (2006): An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter. Published in: IEEE International Conference on Semiconductor Electronics (ICSE) No. 10.1109/SMELEC.2006.380749 (15. May 2006): pp. 811-815.
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The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.
|Item Type:||MPRA Paper|
|Original Title:||An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter|
|Keywords:||Decimation; CIC; comb; Filters; Converters; Sigma Delta A/D conversion; comb filters; decimation filters;|
|Subjects:||F - International Economics > F1 - Trade > F14 - Empirical Studies of Trade
L - Industrial Organization > L7 - Industry Studies: Primary Products and Construction
O - Economic Development, Innovation, Technological Change, and Growth > O1 - Economic Development > O14 - Industrialization ; Manufacturing and Service Industries ; Choice of Technology
|Depositing User:||Rozita Teymourzadeh|
|Date Deposited:||03. Sep 2012 09:49|
|Last Modified:||08. Mar 2015 14:53|
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