An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter

Teymourzadeh, Rozita and Othman, Masuri (2006): An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter. Published in: IEEE International Conference on Semiconductor Electronics (ICSE) No. 10.1109/SMELEC.2006.380749 (15 May 2006): pp. 811-815.

Abstract

The over sampling technique has been shown to increase the SNR and is used in many high performance system such as in the ADC for audio and DAT systems. This paper presents the design of the decimation and its VLSI implementation which is the sub-component in the over sampling technique. The design of three main units in the decimation stage that is the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also described. The Verilog HDL code in Xilinx ISE environment has been derived to describe the CIC filter properties and downloaded in to Virtex II FPGA board. In the design of these units, we focus on the trade-off between the speed improvement and the power consumption as well as the silicon area for the chip implementation.

• Item Type: MPRA Paper
• Language: English
• Keywords: Decimation; CIC; comb; Filters; Converters; Sigma Delta A/D conversion; comb filters; decimation filters
• Subjects: F - International Economics > F1 - Trade > F14 - Empirical Studies of Trade; L - Industrial Organization > L7 - Industry Studies: Primary Products and Construction; O - Economic Development, Innovation, Technological Change, and Growth > O1 - Economic Development > O14 - Industrialization ; Manufacturing and Service Industries ; Choice of Technology

References

[1] T. Ritoniemi, E.Pajarre. S. Ingalsuo, T. Husu, V. Eerola, and T. Saramiiki, “ A Stereo Audio Sigma-delta AD-Converter”. IEEE J. Solid –state Circ., Vol.29, no.12, pp.1514-1523, Dec. (1994).

[2] E.B. Hogenauer, “An Economical Class of digital filters for Decimation and interpolation”, IEEE Transactions on Acoustics, Speech, and Signal Prosessing, Vol. ASSP-29,pp.155-162, April (1981).

[3] S. Park, “Principles of Sigma-delta Modulation for Analog-to-Digital Converters”, Motorola Inc, APR8/D Rev.1, (1990).

[4] A.Garcia, U. Meyer-Baese & F. Taylor, “Pipelined Hogenauer CIC Filters Using Field-Programmable Logic and Residue Number System”. Acoustics, Speech and Signal processing IEEE International Conference,Vol. 5, pp.3085-3088 (1998).

[5] U. Meyer-Baese, S. Rao, J. Ramirez, & A. Garcia, “Cost-effective Hogenauer Cascaded Integrator Comb Decimator Filter Design for custom ICs”. IEE Electronic journal. Vol. 41, no. 3, pp. 158-160 (2005).

[6] P. B. Brandt & A. Bruce. Wooley, “A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation”. IEEE Journal of Solid-State Circuits, Vol. 29, no.6, June (1994).

[7] Y. Djadi and T. A. Kwasniewski, C. Chan and V. Szwarc, “A high throughput Programmable Decimation and Interpolation Filter”, Proceeding of International Conference on Signal Processing Applications and Technology, pp.1743-1748, (1994).

[8] D.M. Ciletti, Advanced Digital design with the Verilog HDL, Prentice Hall, Department of Electrical and Computer Engineering University of Colorado at Colorado Springs, (2003).

[9] S. M. Mortazavi, S. M. Fakhraie & O. Shoaei. “ A Comparative Stydy and Design of Decimation Filter For high-Precision Audio Data Converters”, The 17 IEEE international conference on microelectronics. pp.139-143, (2005).